skidl.net module

Network connection management for SKiDL circuit design.

This module provides comprehensive electrical connection management through the Net class and its specialized subclass NCNet. These classes represent electrical connections between component pins, enabling circuit designers to model, analyze, and verify electrical connectivity in their designs.

Key Capabilities:

• Electrical connection modeling between component pins

• Named and anonymous net creation with automatic naming

• Net merging and electrical rule checking (ERC)

• Drive strength management and conflict detection

• Net class assignment for PCB routing rules

• Hierarchical net traversal and connectivity analysis

• No-connect (NC) net support for unconnected pins

• Integration with netlist generation and PCB tools

Core Classes:

Net: Primary class representing electrical connections between pins.

Supports naming, drive strength, net classes, ERC, and connection management. Handles automatic net merging when pins are connected.

NCNet: Specialized Net subclass for explicitly unconnected pins.

Marks pins as intentionally not connected to suppress ERC warnings while maintaining design intent documentation.

Connection Model:

Nets use a pin-centric connection model where pins can belong to multiple nets simultaneously, enabling complex electrical relationships. When nets are joined (via pin connections), they form electrically connected segments that share properties like drive strength and net classes.

Electrical Rules:

The module supports comprehensive electrical rule checking (ERC) including: - Drive strength conflicts (multiple drivers on one net) - Floating pin detection (inputs without drivers) - No-connect verification (intentionally unconnected pins) - Net class rule validation and conflict resolution

Example Usage:

>>> # Create named and anonymous nets
>>> vcc = Net('VCC')                    # Named power net
>>> gnd = Net('GND')                    # Named ground net
>>> data = Net()                        # Anonymous net (auto-named)
>>>
>>> # Connect component pins to nets
>>> vcc += mcu['VCC'], regulator['OUT'] # Multiple connections
>>> gnd += mcu['GND'], regulator['GND'] # Ground connections
>>> data += mcu['PA0'], sensor['DATA']  # Data connection
>>>
>>> # Create no-connect nets for unused pins
>>> nc = NCNet()                        # No-connect net
>>> nc += mcu['UNUSED1'], mcu['UNUSED2'] # Mark pins as NC
>>>
>>> # Apply net classes for PCB routing
>>> power_class = NetClass('Power', trace_width=0.5, clearance=0.2)
>>> vcc.netclass = power_class          # Apply to power nets
>>>
>>> # Check electrical connectivity
>>> print(f"VCC has {len(vcc)} pins connected")
>>> print(f"Data net name: {data.name}")
>>> if vcc.is_attached(mcu['VCC']):
...     print("MCU VCC pin is connected to VCC net")

Advanced Features:

• Multi-segment nets with automatic name merging

• Drive strength propagation and conflict detection

• Hierarchical net traversal for complex connectivity

• Stub net support for schematic generation

• Network object creation for circuit analysis

• XML and netlist export for PCB tools

• Deep copying with automatic name adjustment

Integration:

Nets integrate seamlessly with other SKiDL components: - Parts: Automatic connection via pin assignments - Buses: Multi-bit connection management - Circuits: Automatic net registration and naming - ERC: Built-in electrical rule checking - Tools: Export to KiCad, Altium, Eagle, etc.

class skidl.net.NCNet(name=None, circuit=None, *pins_nets_buses, **attribs)

Bases: Net

A specialized Net subclass for explicitly marking pins as not connected.

NCNet (No Connect Net) is used to explicitly mark component pins as intentionally unconnected. This serves two important purposes:

1. Design Intent Documentation: Clearly indicates that leaving pins unconnected is intentional rather than an oversight.

2. ERC Suppression: Prevents electrical rule checking from flagging these pins as floating or unconnected errors.

NCNet objects behave like regular nets for connection purposes but have special properties that distinguish them from normal electrical connections. They don’t appear in netlists since they represent the absence of electrical connections rather than actual connections.

Common Use Cases:

• Unused input pins on digital logic devices

• Reserved pins on microcontrollers not used in current design

• Optional features not implemented in current circuit variant

• Test points or debugging pins not connected in production

• Analog inputs not used in specific application configurations

ERC Behavior:

NCNet objects are excluded from normal ERC checking since they explicitly represent intentionally unconnected pins. This prevents false warnings about floating inputs or undriven nets while maintaining design verification for actual electrical connections.

Netlist Generation:

NCNet objects do not generate entries in netlists or connection lists since they represent the explicit absence of connections. PCB tools typically handle no-connect markers through special annotations rather than actual net connections.

Parameters:

• name (str, optional) – Name for the no-connect net. If None, an automatically generated name will be assigned. Multiple pins can share the same NCNet or use separate NCNet instances.

• circuit (Circuit, optional) – The circuit this no-connect net belongs to. If None, uses the default circuit.

• *pins_nets_buses – Pins, nets, or buses to mark as not connected. These will be connected to this NCNet to indicate their no-connect status.

Keyword Arguments:

attribs – Additional attributes for the no-connect net. Note that some attributes like drive strength are automatically set to appropriate values for no-connect nets.

Examples

>>> # Mark individual unused pins as no-connect
>>> nc1 = NCNet()
>>> nc1 += mcu['UNUSED_PA5'], mcu['UNUSED_PA6']
>>>
>>> # Use separate NC nets for different pin groups
>>> analog_nc = NCNet('ANALOG_NC')
>>> digital_nc = NCNet('DIGITAL_NC')
>>> analog_nc += adc['AIN3'], adc['AIN4']
>>> digital_nc += mcu['PB7'], mcu['PB8']
>>>
>>> # Mark test points as no-connect in production
>>> test_nc = NCNet('TEST_NC')
>>> test_nc += test_point_1['PIN'], test_point_2['PIN']
>>>
>>> # Create during component instantiation
>>> mcu = Part('MCU', 'STM32F401')
>>> nc_net = NCNet()
>>> nc_net += mcu['BOOT0'], mcu['NRST']  # Not used in this design

Design Verification:

While NCNet pins are excluded from standard ERC checking, they can still be verified for design intent: - Confirm all NC pins are intentionally unconnected - Verify no required pins are accidentally marked as NC - Check that NC assignments match design specifications

Tool Integration:

Different PCB tools handle no-connect markers differently: - KiCad: No-connect flags on pins, excluded from netlist - Altium: No ERC markers, special netlist handling - Eagle: No-connect symbols, netlist exclusion - Other tools: Tool-specific no-connect representations

Best Practices:

• Use descriptive names for NC nets to document intent

• Group related NC pins on the same NC net when appropriate

• Document why specific pins are marked as no-connect

• Review NC assignments during design reviews

• Consider future design variants that might use NC pins

property drive

Get the drive strength of this no-connect net.

No-connect nets have a fixed drive strength of NOCONNECT that cannot be modified. This special drive value indicates that the net represents intentionally unconnected pins rather than an actual electrical signal.

The NOCONNECT drive strength serves several purposes: - Identifies the net as representing non-connections - Excludes the net from drive conflict checking during ERC - Indicates to tools that this net should not appear in netlists - Documents design intent for unconnected pins

Returns:

Always returns pin_drives.NOCONNECT. This value cannot be

changed for NCNet objects since it represents their fundamental characteristic as no-connect nets.

Return type:

int

Examples

>>> from skidl.pin import pin_drives
>>>
>>> nc_net = NCNet('UNUSED_PINS')
>>> print(nc_net.drive == pin_drives.NOCONNECT)  # True
>>>
>>> # Compare with regular net drive
>>> reg_net = Net('SIGNAL')
>>> reg_net += driver_pin, receiver_pin
>>> print(reg_net.drive != pin_drives.NOCONNECT)  # True
>>>
>>> # Drive strength cannot be changed for NC nets
>>> try:
...     nc_net.drive = pin_drives.STRONG   # This won't work
... except AttributeError:
...     print("NCNet drive cannot be modified")

ERC Integration:

The NOCONNECT drive strength integrates with electrical rule checking: - Pins on NCNet are excluded from floating pin detection - No drive conflict checking is performed for NC nets - ERC reports can identify and verify no-connect assignments - Design verification can confirm intentional non-connections

Immutability:

The drive property for NCNet objects is read-only. Attempting to set or delete the drive strength will not work since the NOCONNECT drive is fundamental to the NCNet’s purpose and behavior.

Tool Compatibility:

The NOCONNECT drive strength is recognized by netlist generators and ERC systems to provide appropriate handling of no-connect nets across different PCB design tools and workflows.

generate_netlist_net(tool=None)

Generate netlist representation for no-connect nets.

No-connect nets intentionally do not appear in circuit netlists since they represent the explicit absence of electrical connections rather than actual circuit connections. This method always returns an empty string to exclude NCNet objects from netlist output.

Parameters:

tool (str, optional) – The target netlist generation tool (e.g., ‘kicad’, ‘altium’, ‘eagle’). Parameter is accepted for compatibility but ignored since NC nets are excluded from all netlist formats.

Returns:

Always returns an empty string. No-connect nets do not generate

netlist entries since they represent intentionally unconnected pins rather than actual electrical connections.

Return type:

str

Examples

>>> nc_net = NCNet('UNUSED_PINS')
>>> nc_net += mcu['PA7'], mcu['PA8']
>>>
>>> # NC nets don't appear in netlists
>>> netlist_entry = nc_net.generate_netlist_net('kicad')
>>> print(repr(netlist_entry))              # ''
>>>
>>> # Compare with regular net
>>> vcc_net = Net('VCC')
>>> vcc_net += mcu['VCC']
>>> vcc_entry = vcc_net.generate_netlist_net('kicad')
>>> print(len(vcc_entry) > 0)               # True

Tool Integration:

Different PCB tools handle no-connect pins through special mechanisms: - Pin-level no-connect flags rather than net-level connections - Special symbols or annotations in schematic capture - ERC rule exclusions for intentionally unconnected pins - Design rule checking modifications for NC pins

Design Verification:

While NC nets don’t appear in netlists, they can still be verified: - Pin assignment reports can show NC pin assignments - ERC reports can list pins marked as no-connect - Design review outputs can document intentional non-connections - BOM generation can identify unused pin functionality

class skidl.net.Net(name=None, circuit=None, *pins_nets_buses, **attribs)

Bases: SkidlBaseObject

Represents an electrical connection between component pins in a circuit.

The Net class is the fundamental building block for electrical connectivity in SKiDL circuits. It manages collections of pins that are electrically connected, handles net naming and drive strength management, supports net classes for PCB routing rules, and provides electrical rule checking (ERC).

Nets can be created with explicit names or receive automatically generated names. They support dynamic connection and disconnection of pins, automatic merging when nets are joined through common pins, and property propagation across connected net segments.

Connection Management:

Nets use the += operator for intuitive pin connection syntax. When pins are connected to nets, the nets automatically merge if the pins were previously connected to other nets, creating larger electrically connected groups.

Drive Strength:

Nets automatically track and manage drive strength based on connected pins. Drive conflicts (multiple strong drivers) are detected and can be flagged during ERC. The net’s drive strength is always the maximum of all connected pins.

Net Classes:

Nets can be assigned to one or more net classes that define PCB routing rules, trace widths, clearances, via sizes, and other physical properties. These are used during PCB layout and design rule checking.

Electrical Rules:

Built-in ERC functions check for common electrical problems including floating inputs, drive conflicts, and design rule violations. Custom ERC functions can be added for specific design requirements.

Parameters:

• name (str, optional) – Explicit name for the net. If None or empty, an automatically generated unique name will be assigned using the NET_PREFIX pattern (e.g., “N$1”, “N$2”, etc.).

• circuit (Circuit, optional) – The circuit this net belongs to. If None, the net is added to the default active circuit.

• *pins_nets_buses – Initial pins, nets, or buses to connect to this net. Can be individual objects or collections. Nets will be merged if pins connect previously separate nets.

Keyword Arguments:

attribs – Arbitrary keyword=value attributes to attach to the net. Common attributes include drive strength overrides, ERC flags, documentation strings, and tool-specific properties.

Examples

>>> # Create named nets for power and ground
>>> vcc = Net('VCC')           # 3.3V power rail
>>> gnd = Net('GND')           # Ground reference
>>>
>>> # Create anonymous nets (auto-named)
>>> data_net = Net()           # Becomes "N$1"
>>> clock_net = Net()          # Becomes "N$2"
>>>
>>> # Connect pins during creation
>>> spi_clk = Net('SPI_CLK', mcu['SCK'], flash['CLK'])
>>>
>>> # Connect pins after creation
>>> data_net += mcu['PA0']     # Connect single pin
>>> data_net += sensor['OUT'], led['IN']  # Connect multiple pins
>>>
>>> # Apply net classes for PCB routing
>>> power_class = NetClass('Power', trace_width=0.5)
>>> vcc.netclass = power_class
>>>
>>> # Check connections and properties
>>> print(f"VCC net has {len(vcc)} pins")
>>> print(f"Drive strength: {vcc.drive}")
>>> if vcc.is_attached(mcu['VCC']):
...     print("MCU VCC pin is on VCC net")

Advanced Usage:

>>> # Create multiple copies for arrays
>>> data_buses = 8 * Net('DATA')  # Creates DATA_0 through DATA_7
>>>
>>> # Merge nets by connecting common pins
>>> net1 = Net('SIGNAL_A')
>>> net2 = Net('SIGNAL_B')
>>> shared_pin = mcu['PA1']
>>> net1 += shared_pin     # Pin on net1
>>> net2 += shared_pin     # Merges net1 and net2
>>>
>>> # Use in network analysis
>>> network = net1.create_network()  # Convert to Network object
>>>
>>> # Export for PCB tools
>>> netlist_data = vcc.generate_netlist_net('kicad')

connect(*pins_nets_buses)

Connect pins, nets, and buses to this net, creating electrical connections.

This is the primary method for building electrical connectivity in SKiDL circuits. It handles connecting individual pins, merging nets, and expanding buses into individual connections. When nets are connected through common pins, they automatically merge into larger electrically connected groups.

The method supports the += operator for intuitive connection syntax and handles all the complexity of maintaining electrical connectivity, drive strength propagation, and net class inheritance across connected segments.

Parameters:

*pins_nets_buses – Objects to connect to this net: - Pin: Individual component pins to attach - Net: Other nets to merge with this one - Bus: Multi-bit collections (individual nets extracted) - Lists/tuples: Collections of the above objects - None values: Ignored for programming convenience

Returns:

This net object (supports method chaining and += operator).

Return type:

Net

Raises:

• ValueError – If attempting to connect nets from different circuits. All connected objects must belong to the same circuit context.

• ValueError – If attempting to connect parts from different circuits. Component pins must be from parts in the same circuit.

• TypeError – If attempting to connect unsupported object types. Only Pin, Net, and Bus objects can be connected to nets.

Examples

>>> # Connect individual pins
>>> vcc = Net('VCC')
>>> vcc.connect(mcu['VCC'], regulator['OUT'])
>>>
>>> # Use += operator (equivalent to connect)
>>> gnd = Net('GND')
>>> gnd += mcu['GND'], regulator['GND'], capacitor[2]
>>>
>>> # Connect nets (automatic merging)
>>> signal_a = Net('SIG_A')
>>> signal_b = Net('SIG_B')
>>> shared_pin = buffer['OUT']
>>> signal_a += shared_pin        # Pin on signal_a
>>> signal_b += shared_pin        # Merges signal_a and signal_b
>>>
>>> # Connect buses (expanded automatically)
>>> data_bus = Bus('DATA', 8)     # 8-bit bus
>>> control_net = Net('CTRL')
>>> control_net += data_bus[0]    # Connect to bit 0 of bus
>>>
>>> # Chain connections
>>> clock_net = Net('CLK').connect(mcu['CLK'], rtc['CLK_OUT'])

Net Merging:

When connecting nets that already have pins attached, the nets automatically merge into a single electrical group. All properties like drive strength and net classes are combined according to precedence rules (maximum drive, class union, etc.).

Drive Strength:

Connected pins contribute their drive strength to the net. The net’s overall drive is the maximum of all connected pins. Drive conflicts (multiple strong drivers) are detected during ERC checking.

Net Classes:

When nets are merged, their net classes are combined. If conflicting net classes are detected, warnings may be issued depending on the specific class definitions and priority levels.

Circuit Validation:

All connected objects must belong to the same circuit. Cross-circuit connections are not allowed and will raise ValueError exceptions. This maintains circuit encapsulation and prevents invalid topologies.

copy(num_copies=None, circuit=None, **attribs)

Create one or more copies of this net.

Parameters:

• num_copies (int, optional) – Number of copies to create. If None, a single copy will be made.

• circuit (Circuit, optional) – The circuit the copies will be added to.

• **attribs – Attributes to apply to the copies.

Returns:

A single Net copy or list of copies.

Return type:

Net or list[Net]

Raises:

• ValueError – If num_copies is not a non-negative integer.

• ValueError – If trying to copy a net that already has pins attached.

Examples

>>> n = Net('A')    # Create a net.
>>> n_copy = n()    # Copy the net.
>>> n_array = 10 * Net('A')  # Create an array of 10 nets.

create_network()

Create a Network object containing just this net.

Returns:

A network containing this net.

Return type:

Network

disconnect(pin)

Remove a pin from this net but not from other nets it’s attached to.

Parameters:

pin (Pin) – The pin to disconnect from this net.

property drive

Get, set or delete the drive strength of this net.

The drive strength represents the electrical driving capability of the net. It is automatically set to the maximum drive value of any pin connected to the net, and cannot be set to a lower value than the current maximum.

Returns:

The drive strength value.

Return type:

int

erc_list = [<function dflt_net_erc>]

classmethod fetch(name, *args, **attribs)

Get an existing net by name, or create it if not found.

This convenience method combines the functionality of get() and __init__() to provide a “get-or-create” pattern. It first attempts to find an existing net with the specified name, and if not found, creates a new net with that name and the provided parameters.

This is particularly useful for building circuits where you want to reference nets by name without worrying about whether they already exist, such as when importing from netlists or building circuits procedurally.

Parameters:

• name (str) – Name of the net to fetch or create. Used for both the search (if net exists) and the name parameter (if creating).

• *args – Additional positional arguments passed to Net() constructor if creation is needed. Ignored if net already exists.

• **attribs – Keyword arguments passed to Net() constructor if creation is needed. The ‘circuit’ parameter is used for both search and creation contexts.

Returns:

Either the existing net with the specified name, or a newly

created net if no existing net was found. The returned net is guaranteed to have the requested name (or a unique variant).

Return type:

Net

Examples

>>> # Basic fetch-or-create pattern
>>> vcc = Net.fetch('VCC')                  # Creates if not exists
>>> vcc2 = Net.fetch('VCC')                 # Returns existing net
>>> assert vcc is vcc2                     # Same object
>>>
>>> # Fetch with creation parameters
>>> power = Net.fetch('POWER_RAIL',
...                   mcu['VCC'], regulator['OUT'],  # Initial connections
...                   do_erc=True,                   # ERC enabled
...                   circuit=main_circuit)          # Specific circuit
>>>
>>> # Use in circuit building
>>> def connect_power(part):
...     vcc = Net.fetch('VCC')              # Always get VCC net
...     gnd = Net.fetch('GND')              # Always get GND net
...     vcc += part['VCC']                  # Connect power
...     gnd += part['GND']                  # Connect ground
>>>
>>> # Procedural circuit construction
>>> for i in range(8):
...     data_net = Net.fetch(f'DATA_{i}')
...     data_net += processor[f'D{i}'], memory[f'D{i}']

Creation vs. Retrieval:

• If a net with the specified name exists: Returns existing net, ignores all other parameters

• If no net exists: Creates new net with all provided parameters

• Circuit context: Used for both search and creation

Name Uniqueness:

If the requested name conflicts with existing nets during creation, the new net will receive a modified name (e.g., “VCC_1”, “VCC_2”) to maintain uniqueness within the circuit.

Circuit Handling:

The ‘circuit’ parameter serves dual purposes: - Search context: Where to look for existing nets - Creation context: Where to create new nets if needed - If not specified, uses the default circuit for both operations

Error Handling:

Creation errors (invalid parameters, circuit conflicts, etc.) are passed through from the Net() constructor. Retrieval errors are rare since get() returns None for missing nets rather than raising exceptions.

Use Cases:

• Importing circuits from external netlists

• Procedural circuit generation with named nets

• Building reusable circuit functions that reference standard nets

• Interactive circuit construction where net existence is uncertain

generate_netlist_net(tool=None)

Generate the net information for inclusion in a netlist.

Parameters:

tool (str, optional) – The format for the netlist file (e.g., KICAD).

Returns:

The net information formatted for the specified tool.

Return type:

str

generate_xml_net(tool=None)

Generate the net information for inclusion in an XML file.

Parameters:

tool (str, optional) – The format for the XML file (e.g., KICAD).

Returns:

The net information formatted as XML for the specified tool.

Return type:

str

classmethod get(name, circuit=None)

Retrieve an existing net by name from a circuit.

Searches the specified circuit (or default circuit) for a net with the given name or alias. This provides a convenient way to access existing nets without maintaining explicit references, especially useful in hierarchical designs or when working with imported netlists.

The search examines both primary net names and any assigned aliases, using string matching to find the best match. Case-sensitive exact matching is performed for reliable net identification.

Parameters:

• name (str) – Name or alias of the net to find. Must match exactly (case-sensitive) either the net’s primary name or one of its assigned aliases.

• circuit (Circuit, optional) – Circuit to search for the net. If None, searches the currently active default circuit.

Returns:

The found Net object if a match is found, otherwise

None. For nets with multiple interconnected segments, returns the first segment found (all segments share the same name).

Return type:

Net or None

Examples

>>> # Find nets by primary name
>>> vcc = Net.get('VCC')                    # Find VCC net
>>> ground = Net.get('GND', my_circuit)     # Find in specific circuit
>>>
>>> # Find nets by alias
>>> power = Net.get('POWER_RAIL')           # Might be alias for VCC
>>>
>>> # Handle missing nets gracefully
>>> test_net = Net.get('TEST_SIGNAL')
>>> if test_net is None:
...     print("Test signal net not found")
... else:
...     print(f"Found net with {len(test_net)} pins")
>>>
>>> # Use in conditional operations
>>> existing_clk = Net.get('CLK') or Net('CLK')  # Get or create

Search Strategy:

The method searches in the following order: 1. Primary net names (exact string match) 2. Net aliases (exact string match) 3. Returns None if no matches found

Multi-segment Nets:

For nets composed of multiple interconnected segments (created by merging nets), the search returns the first segment found. All segments of a multi-segment net share the same name, so any segment provides access to the complete electrical group.

Circuit Context:

Each circuit maintains its own namespace for net names. The same name can exist in different circuits without conflict. Always specify the circuit parameter when working with multiple circuits to ensure you get the net from the correct context.

Performance:

The search is optimized for typical circuit sizes but may be slower for very large circuits with thousands of nets. Consider maintaining direct references for frequently accessed nets in performance-critical applications.

get_nets()

Get all connected net segments including this one.

Returns:

List of all net segments connected to this net, including this net.

Return type:

list

get_pins()

Get all pins connected to this net.

Returns:

List of pins attached to this net, including pins attached

to electrically connected segments.

Return type:

list

is_attached(pin_net_bus)

Check if a pin, net, or bus is electrically connected to this net.

Parameters:

pin_net_bus – A Pin, Net, or Bus object to check for attachment.

Returns:

True if the object is electrically connected to this net.

Return type:

bool

Raises:

TypeError – If the given object is not a Pin, Net, or Bus.

is_implicit()

Check if the net has an implicitly generated name.

Implicit net names start with NET_PREFIX or BUS_PREFIX.

Returns:

True if the net name is implicitly generated.

Return type:

bool

is_movable()

Check if the net can be moved to another circuit.

A net is movable if it’s not part of a Circuit or if it has no pins attached to it.

Returns:

True if the net is movable.

Return type:

bool

merge_names()

For multi-segment nets, select a common name for all segments.

When nets are joined, they can have different names. This method chooses the best name among connected net segments and assigns it to all of them.

property name

Get or set the name of this net.

When setting the net name, if another net with the same name exists in the circuit, the name for this net will be adjusted to make it unique.

Returns:

Net name.

Return type:

str

property netclasses

Get or set the net class(es) assigned to this net and connected segments.

Net classes define PCB routing rules including trace widths, clearances, via sizes, and electrical properties. They control how nets are routed during PCB layout and enforce design constraints. A net can be assigned to multiple net classes for complex routing requirements.

When setting net classes, the assignment automatically propagates to all electrically connected net segments, ensuring consistent routing rules across the entire electrical connection. This maintains design integrity when nets are merged or split during circuit construction.

Returns:

Container holding zero or more NetClass objects. An empty list indicates no net class assignments. The container supports iteration, indexing, and membership testing for convenient access to assigned classes.

Return type:

NetClasses

Examples

>>> # Check current net class assignments
>>> power_net = Net('VCC')
>>> print(len(power_net.netclass))          # 0 (no classes assigned)
>>>
>>> # Assign single net class
>>> power_class = NetClass('Power', trace_width=0.5, clearance=0.2)
>>> power_net.netclass = power_class
>>> print(len(power_net.netclass))          # 1
>>> print(power_net.netclass[0].name)       # 'Power'
>>>
>>> # Assign multiple net classes
>>> critical_class = NetClass('Critical', priority=1)
>>> power_net.netclass = power_class, critical_class
>>> print(len(power_net.netclass))          # 2
>>>
>>> # Check for specific class membership
>>> if power_class in power_net.netclass:
...     print(f"Net uses {power_class.name} routing rules")
>>>
>>> # Iterate through assigned classes
>>> for nc in power_net.netclass:
...     print(f"Class: {nc.name}, Width: {nc.trace_width}mm")

Multi-segment Propagation:

When nets are electrically connected through shared pins, all segments automatically share the same net class assignments:

>>> net1 = Net('SIG_A')
>>> net2 = Net('SIG_B')
>>> net1.netclass = power_class          # Assign to net1
>>> shared_pin = mcu['PA1']
>>> net1 += shared_pin                   # Connect pin to net1
>>> net2 += shared_pin                   # Merges nets, shares classes
>>> print(net2.netclass == net1.netclass)  # True

Class Conflict Resolution:

Multiple net classes with conflicting properties are resolved based on priority levels and tool-specific rules. Classes with higher priority numbers typically override lower priority classes:

>>> low_priority = NetClass('Critical', priority=1, trace_width=0.8)
>>> high_priority = NetClass('Standard', priority=10, trace_width=0.3)
>>> signal_net.netclass = high_priority, low_priority
>>> # PCB tool will likely use 0.8mm width from high_priority class

Assignment Operations:

Net class assignments are additive by default - new classes are added to existing assignments rather than replacing them:

>>> signal_net.netclass = class1         # Assign first class
>>> signal_net.netclass = class2         # Add second class
>>> print(len(signal_net.netclass))      # 2 (both classes assigned)
>>>
>>> # To replace all classes, delete first
>>> del signal_net.netclass              # Clear all classes
>>> signal_net.netclass = new_class      # Assign replacement

PCB Tool Integration:

Net class assignments are exported during netlist generation and become design rules in PCB layout tools. Different tools handle multiple classes differently - some merge properties, others use priority-based selection, and some apply all rules simultaneously.

Design Rule Checking:

Net classes enable automated design rule checking (DRC) during PCB layout. Violations of trace width, clearance, or via size rules generate errors that must be resolved before manufacturing.

property nets

Get all net segments connected to this net.

Returns:

List of all net segments electrically connected to this net.

Return type:

list

property pins

Get the pins attached to this net.

Returns:

List of pins attached to this net.

Return type:

list

property stub

Get or set the stub status of this net.

A stub net is not routed in schematic generation, but is represented as a short stub connected to the pin.

Returns:

True if this is a stub net.

Return type:

bool

test_validity()

Test if the net is valid for use.

Raises:

ValueError – If the net is no longer valid.

property valid

Check if this net is still valid.

Returns:

True if the net is valid, False if it has been invalidated.

Return type:

bool

property width

Get the width of the net.

Returns:

Always 1 for a Net object.

Return type:

int