skidl.circuit module

Circuit management in SKiDL.

This module provides the Circuit class which serves as the central container for all circuit elements (parts, nets, buses) and their interconnections. It handles hierarchical circuit structures, electrical rule checking (ERC), and output generation (netlists, PCBs, SVGs, etc.).

class skidl.circuit.Circuit(**attrs)[source]

Bases: SkidlBaseObject

Container for an entire electronic circuit design.

The Circuit class is the central repository for all the parts, nets, buses, and interfaces that make up a circuit. It manages the hierarchical structure of the design, performs electrical rule checking, and generates various outputs like netlists, PCB files, and graphical representations.

parts

List of all parts in the circuit.

Type:

list

nets

List of all nets in the circuit.

Type:

list

buses

List of all buses in the circuit.

Type:

list

interfaces

List of all interfaces in the circuit.

Type:

list

hierarchy

Current position in the hierarchy, represented as a dot-separated string.

Type:

str

level

Current level in the hierarchy.

Type:

int

context

Stack tracking the context at each hierarchical level.

Type:

list

erc_list

List of ERC (Electrical Rule Checking) functions to run on the circuit.

Type:

list

NC

The special no-connect net used in this circuit.

Type:

Net

ERC(*args, **kwargs)[source]

Perform Electrical Rule Checking on the circuit.

This method runs both the class-wide ERC functions and any local ERC functions defined for this circuit. It checks for issues like unconnected pins, pin type conflicts, etc.

Parameters:

  • *args – Arguments to pass to the ERC functions.

  • **kwargs – Keyword arguments to pass to the ERC functions.

activate(node)[source]

Activate a node in the circuit hierarchy.

This method adds the given node to the circuit’s node set, establishes parent-child relationships in the hierarchy, and sets it as the current active node.

Parameters:

node (Node) – The node instance to activate.

Returns:

The activated node instance.

Return type:

Node

Note

If an active node already exists, the new node becomes its child. The new node then becomes the active node for subsequent operations.

add_buses(*buses)[source]

Add buses to the circuit.

Parameters:

*buses – Bus objects to add to the circuit.

Raises:

ValueError – If attempting to add an unmovable bus.

add_netclasses(*netclasses)[source]

Add one or more net classes to the circuit.

Parameters:

*netclasses – One or more net classes to add to the circuit.

add_nets(*nets)[source]

Add nets to the circuit.

Parameters:

*nets – Net objects to add to the circuit.

Raises:

ValueError – If attempting to add an unmovable net.

add_partclasses(*partclasses)[source]

Add one or more part classes to the circuit.

Parameters:

*partclasses – One or more part classes to add to the circuit.

add_parts(*parts)[source]

Add parts to the circuit.

Parameters:

*parts – Part objects to add to the circuit.

Raises:

ValueError – If attempting to add an unmovable part.

add_stuff(*stuff)[source]

Add various circuit elements to the circuit.

Parameters:

*stuff – Parts, nets, buses, or interfaces to add.

Returns:

The updated circuit.

Return type:

Circuit

Raises:

ValueError – If attempting to add an unsupported type.

backup_parts(file_=None)[source]

Save all parts in the circuit as a SKiDL library file.

This creates a backup library that can be used to restore the parts in the circuit.

Parameters:

file (str or file object, optional) – File to write the library to. If None, a standard library file will be used.

check_for_empty_footprints()[source]

Check that all parts have assigned footprints.

This method calls the empty_footprint_handler for any parts that don’t have a footprint assigned.

check_tags()[source]

Check for missing part or hierarchical node tags.

Tags are important for maintaining stable associations between schematic parts and PCB footprints. This method warns about any missing tags.

cull_unconnected_parts()[source]

Remove parts that aren’t connected to anything in the circuit.

This can be useful to clean up a design by removing unused parts.

deactivate()[source]

Deactivate the current hierarchical node and return to its parent.

This method moves up one level in the circuit hierarchy by setting the active node to its parent. The circuitry created within the current hierarchical level remains intact in the part and net lists, but the hierarchical context is restored to the previous level.

Returns:

None

Note

This method does not remove any circuit components or connections that were added while the current node was active.

erc_list = [<function dflt_circuit_erc>]
generate_dot(file_=None, engine='neato', rankdir='LR', part_shape='rectangle', net_shape='point', splines=None, show_values=True, show_anon=False, split_nets=['GND'], split_parts_ref=[])[source]

Generate a Graphviz DOT visualization of the circuit.

Creates a graphical representation of the circuit as a graph where parts and nets are nodes, and connections are edges.

Parameters:

  • file (str, optional) – File to write the DOT data to.

  • engine (str, optional) – Graphviz layout engine to use. Default is “neato”.

  • rankdir (str, optional) – Direction of graph layout. Default is “LR” (left to right).

  • part_shape (str, optional) – Shape to use for part nodes. Default is “rectangle”.

  • net_shape (str, optional) – Shape to use for net nodes. Default is “point”.

  • splines (str, optional) – Style for the edges. Try “ortho” for schematic-like feel.

  • show_values (bool, optional) – Show part values as labels. Default is True.

  • show_anon (bool, optional) – Show anonymous net names. Default is False.

  • split_nets (list, optional) – List of net names to split in visualization. Default is [“GND”].

  • split_parts_ref (list, optional) – List of part references to split in visualization.

Returns:

A Graphviz graph object.

Return type:

graphviz.Digraph

generate_graph(file_=None, engine='neato', rankdir='LR', part_shape='rectangle', net_shape='point', splines=None, show_values=True, show_anon=False, split_nets=['GND'], split_parts_ref=[])

Generate a Graphviz DOT visualization of the circuit.

Creates a graphical representation of the circuit as a graph where parts and nets are nodes, and connections are edges.

Parameters:

  • file (str, optional) – File to write the DOT data to.

  • engine (str, optional) – Graphviz layout engine to use. Default is “neato”.

  • rankdir (str, optional) – Direction of graph layout. Default is “LR” (left to right).

  • part_shape (str, optional) – Shape to use for part nodes. Default is “rectangle”.

  • net_shape (str, optional) – Shape to use for net nodes. Default is “point”.

  • splines (str, optional) – Style for the edges. Try “ortho” for schematic-like feel.

  • show_values (bool, optional) – Show part values as labels. Default is True.

  • show_anon (bool, optional) – Show anonymous net names. Default is False.

  • split_nets (list, optional) – List of net names to split in visualization. Default is [“GND”].

  • split_parts_ref (list, optional) – List of part references to split in visualization.

Returns:

A Graphviz graph object.

Return type:

graphviz.Digraph

generate_netlist(**kwargs)[source]

Generate a netlist for the circuit.

Parameters:

  • file (str or file object, optional) – File to write netlist to.

  • tool (str, optional) – The EDA tool to generate the netlist for.

  • do_backup (bool, optional) – If True, create a library with all parts in the circuit.

  • **kwargs – Additional arguments passed to the tool-specific netlist generator.

Returns:

The generated netlist as a string.

Return type:

str

generate_netlistsvg_skin(net_stubs, layout_options=None)[source]

Generate SVG for schematic symbols for a netlistsvg skin file.

This creates the SVG symbol definitions that will be used by netlistsvg to visualize the circuit.

Parameters:
Returns:

SVG content for the skin file.

Return type:

str

generate_pcb(**kwargs)[source]

Create a PCB file from the circuit.

Parameters:

  • file (str or file object, optional) – File to write PCB data to.

  • tool (str, optional) – The EDA tool to generate the PCB for.

  • do_backup (bool, optional) – If True, create a library with all parts in the circuit.

  • fp_libs (list, optional) – List of directories containing footprint libraries.

  • **kwargs – Additional arguments passed to the tool-specific PCB generator.

generate_schematic(**kwargs)[source]

Create a schematic file from the circuit.

This generates a visual representation of the circuit that can be opened in an EDA tool like KiCad’s Eeschema.

Parameters:

**kwargs – Arguments for the schematic generator including: empty_footprint_handler (function, optional): Custom handler for parts without footprints. tool (str, optional): The EDA tool to generate the schematic for.

generate_svg(file_=None, tool=None, layout_options=None)[source]

Create an SVG visualization of the circuit and return the netlistsvg input data.

Parameters:

  • file (str, optional) – Base filename to store SVG and intermediate files.

  • tool (str, optional) – Backend tool to use.

  • layout_options (str, optional) – Options to control netlistsvg/ELK layout algorithm.

Returns:

JSON dictionary that can be used as input to netlistsvg.

Return type:

dict

generate_xml(file_=None, tool=None)[source]

Generate an XML representation of the circuit.

Parameters:

  • file (str or file object, optional) – File to write XML data to.

  • tool (str, optional) – Backend tool to use for XML generation.

Returns:

The generated XML as a string.

Return type:

str

get_net_nc_stubs()[source]

Get all nets/buses that are stubs or no-connects.

Returns:

List of nets that are stubs or no-connects.

Return type:

list

get_nets()[source]

Get all distinct nets in the circuit.

This excludes the no-connect net, empty nets, and nets that are electrically connected to other nets already in the result list.

Returns:

List of distinct nets in the circuit.

Return type:

list

get_node_names()[source]

Get the hierarchical names of all subcircuits/groups in the hierarchy.

Returns:

Tuple of hierarchical node names in the circuit hierarchy.

Return type:

tuple

merge_net_names()[source]

Assign the same name to all segments of multi-segment nets.

This ensures that connected nets share a common name.

merge_nets()[source]

Merge multi-segment nets into a single net.

Note: Multi-segment nets had to be merged or else tests to detect the

same net would fail in routing.py when generating schematics. But as a result of merging, net variables can become invalid because of new merging. Therefore, only do this when generating schematics so other generate_*() functions will not be affected.

mini_reset(init=False)[source]

Reset the circuit to its initial state while preserving certain attributes. This method reinitializes most circuit attributes to their default values, including clearing parts, nets, buses, interfaces, and design classes. It also resets counters and creates a new no-connect net. :param init: If True, indicates this is being called during

initialization. If False (default), additional setup is performed for the default circuit’s global no-connect net.

Note

  • The circuit_stack is only initialized if it doesn’t already exist

  • When init=False and this is the default circuit, the global NC (no-connect) net is updated

  • All unique name heaps are cleared via reset_get_unique_name()

property netclasses

Get the netclasses dictionary for this circuit.

Returns:

A dictionary containing the netclasses defined for this circuit.

Return type:

dict

property no_files

Control whether output files are generated.

Returns:

True if file output is suppressed, False otherwise.

Return type:

bool

property partclasses

Get the dictionary of part classes available in this circuit.

Returns:

A dictionary mapping part class names to their corresponding

part class objects.

Return type:

dict

reset(init=False)[source]

Clear any circuitry and cached part libraries and start over.

Parameters:

init (bool, optional) – True if this is being called during initialization.

rmv_buses(*buses)[source]

Remove buses from the circuit.

Parameters:

*buses – Bus objects to remove from the circuit.

Raises:

ValueError – If attempting to remove an unmovable bus.

rmv_nets(*nets)[source]

Remove nets from the circuit.

Parameters:

*nets – Net objects to remove from the circuit.

Raises:

ValueError – If attempting to remove an unmovable net.

rmv_parts(*parts)[source]

Remove parts from the circuit.

Parameters:

*parts – Part objects to remove from the circuit.

Raises:

ValueError – If attempting to remove an unmovable part.

rmv_stuff(*stuff)[source]

Remove various circuit elements from the circuit.

Parameters:

*stuff – Parts, nets, buses, or interfaces to remove.

Returns:

The updated circuit.

Return type:

Circuit

Raises:

ValueError – If attempting to remove an unsupported type.

to_tuple()[source]

Create a nested tuple representation of the circuit for comparison.

The tuple contains sorted tuples of parts and nets information, suitable for comparing circuits structurally.

Returns:

A tuple containing:

  • A tuple of part representations (ref, name, lib)

  • A tuple of net representations (name, pins)

Return type:

tuple