skidl.skidl module

SKiDL: A Python-Based Schematic Design Language

This module is the main entry point for SKiDL and provides global functions and configuration for creating electronic circuit designs programmatically. It initializes the default circuit and provides functions that operate on it.

skidl.skidl.ERC(*args, **kwargs)

Perform Electrical Rule Checking on the circuit.

This method runs both the class-wide ERC functions and any local ERC functions defined for this circuit. It checks for issues like unconnected pins, pin type conflicts, etc.

Parameters:

  • *args – Arguments to pass to the ERC functions.

  • **kwargs – Keyword arguments to pass to the ERC functions.

skidl.skidl.backup_parts()

Save all parts in the circuit as a SKiDL library file.

This creates a backup library that can be used to restore the parts in the circuit.

Parameters:

file (str or file object, optional) – File to write the library to. If None, a standard library file will be used.

skidl.skidl.empty_footprint_handler(part)

Handle the situation of a Part with no footprint when generating netlist/PCB.

Parameters:

part (Part) – The part with no footprint.

Note

By default, this function logs an error message if the footprint is missing. Override this function if you want to try and set some default footprint for particular types of parts (such as using an 0805 footprint for a resistor).

skidl.skidl.erc_assert()

Add an ERC assertion to this object or its class.

Parameters:

  • assertion – A string containing a Python expression that should evaluate to True.

  • fail_msg – Message to display if assertion fails.

  • severity – Level of severity (ERROR, WARNING, or OK) if assertion fails.

skidl.skidl.generate_dot(splines='neato', show_values='LR', show_anon='rectangle', split_nets='point', split_parts_ref=None)

Generate a Graphviz DOT visualization of the circuit.

Creates a graphical representation of the circuit as a graph where parts and nets are nodes, and connections are edges.

Parameters:

  • file (str, optional) – File to write the DOT data to.

  • engine (str, optional) – Graphviz layout engine to use. Default is “neato”.

  • rankdir (str, optional) – Direction of graph layout. Default is “LR” (left to right).

  • part_shape (str, optional) – Shape to use for part nodes. Default is “rectangle”.

  • net_shape (str, optional) – Shape to use for net nodes. Default is “point”.

  • splines (str, optional) – Style for the edges. Try “ortho” for schematic-like feel.

  • show_values (bool, optional) – Show part values as labels. Default is True.

  • show_anon (bool, optional) – Show anonymous net names. Default is False.

  • split_nets (list, optional) – List of net names to split in visualization. Default is [“GND”].

  • split_parts_ref (list, optional) – List of part references to split in visualization.

Returns:

A Graphviz graph object.

Return type:

graphviz.Digraph

skidl.skidl.generate_graph(show_values='neato', show_anon='LR', split_nets='rectangle', split_parts_ref='point')

Generate a Graphviz DOT visualization of the circuit.

Creates a graphical representation of the circuit as a graph where parts and nets are nodes, and connections are edges.

Parameters:

  • file (str, optional) – File to write the DOT data to.

  • engine (str, optional) – Graphviz layout engine to use. Default is “neato”.

  • rankdir (str, optional) – Direction of graph layout. Default is “LR” (left to right).

  • part_shape (str, optional) – Shape to use for part nodes. Default is “rectangle”.

  • net_shape (str, optional) – Shape to use for net nodes. Default is “point”.

  • splines (str, optional) – Style for the edges. Try “ortho” for schematic-like feel.

  • show_values (bool, optional) – Show part values as labels. Default is True.

  • show_anon (bool, optional) – Show anonymous net names. Default is False.

  • split_nets (list, optional) – List of net names to split in visualization. Default is [“GND”].

  • split_parts_ref (list, optional) – List of part references to split in visualization.

Returns:

A Graphviz graph object.

Return type:

graphviz.Digraph

skidl.skidl.generate_netlist(**kwargs)

Generate a netlist for the circuit.

Parameters:

  • file (str or file object, optional) – File to write netlist to.

  • file – Same as file arg. Kept for backward compatibility.

  • tool (str, optional) – The EDA tool to generate the netlist for.

  • do_backup (bool, optional) – If True, create a library with all parts in the circuit.

  • **kwargs – Additional arguments passed to the tool-specific netlist generator.

Returns:

The generated netlist as a string.

Return type:

str

skidl.skidl.generate_pcb(**kwargs)

Create a PCB file from the circuit.

Parameters:

  • file (str or file object, optional) – File to write PCB data to.

  • tool (str, optional) – The EDA tool to generate the PCB for.

  • do_backup (bool, optional) – If True, create a library with all parts in the circuit.

  • fp_libs (list, optional) – List of directories containing footprint libraries.

  • **kwargs – Additional arguments passed to the tool-specific PCB generator.

skidl.skidl.generate_schematic(**kwargs)

Create a schematic file from the circuit.

This generates a visual representation of the circuit that can be opened in an EDA tool like KiCad’s Eeschema.

Parameters:

**kwargs –

Arguments for the schematic generator including: empty_footprint_handler (function, optional): Custom handler for parts without footprints. tool (str, optional): The EDA tool to generate the schematic for.

KiCad 6 through 10 are supported. KiCad 5 is not: it needs the legacy EESCHEMA .sch format, so passing KICAD5 raises a ValueError. Its other outputs (netlist, PCB, XML) are unaffected.

skidl.skidl.generate_svg(**kwargs)

Create a static SVG drawing of the circuit.

The SVG is a rendering of the same placed-and-routed schematic that generate_schematic() produces, so the two agree on layout. A hierarchical circuit becomes one linked page per sheet: a child sheet appears in its parent as a hyperlinked rectangle, and each child page links back to its parent and to the top sheet. Use flatness=1.0 to collapse the whole design onto a single page instead.

Parameters:

**kwargs –

Arguments for the SVG generator including: file_ (str, optional): Base name for the output files.

Deprecated alias for top_name.

tool (str, optional): The EDA tool whose symbol libraries the

drawing is based on. KiCad 6 through 10 are supported; passing KICAD5 raises a ValueError.

filepath (str, optional): Directory to write the .svg files to. flatness (float, optional): 0.0 (a page per subcircuit, the

default) through 1.0 (everything on one page).

Returns:

The directory the SVG files were written to. The top sheet is <top_name>.svg; a hierarchical circuit adds one file per sheet.

Return type:

str

skidl.skidl.generate_xml()

Generate an XML representation of the circuit.

Parameters:

  • file (str or file object, optional) – File to write XML data to.

  • tool (str, optional) – Backend tool to use for XML generation.

Returns:

The generated XML as a string.

Return type:

str

skidl.skidl.get_default_tool()[source]

Get the ECAD tool that will be used by default.

Returns:

The currently configured default ECAD tool.

skidl.skidl.reset()

Clear any circuitry and cached part libraries and start over.

Parameters:

init (bool, optional) – True if this is being called during initialization.

skidl.skidl.set_default_tool(tool)[source]

Set the ECAD tool that will be used by default.

Parameters:

tool – The ECAD tool to use as the default.